1. Technical Field
The present invention relates to a polishing agent, a polishing method, and an additive liquid for polishing. More specifically, the present invention relates to a polishing agent for chemical mechanical polishing in the production of a semiconductor integrated circuit, a polishing method using the polishing agent, and an additive liquid for polishing for preparing the polishing agent.
2. Background Art
In recent years, along with high integration and high functionality of a semiconductor integrated circuit, a microfabrication technique for realizing miniaturization and high densification of a semiconductor device is under development. Conventionally, in the production of a semiconductor integrated circuit device (hereinafter, sometimes referred to as “semiconductor device”), an inter-level dielectric film, an embedded interconnection, etc. have been planarized using a chemical mechanical polishing (hereinafter, referred to as CMP) method so as to prevent a problem that, for example, unevenness (difference in level) on the layer surface exceeds the depth of focus of lithography and sufficient resolution is not obtained. As the requirement for high refinement or miniaturization of a device becomes stricter, the importance of advanced planarization using CMP is more increasing.
Furthermore, in the production of a semiconductor device, Shallow Trench Isolation (hereinafter, referred to as STI) with a small device isolation width has been recently introduced so as to advance more sophisticated miniaturization of a semiconductor device.
The STI is a technique of forming a trench (groove) on a silicon substrate and filling the trench with an insulating film, thereby forming an electrically insulated device region. In the STI, first, as shown in FIG. 1A, after masking a device region of a silicon substrate 1 with a silicon nitride film 2, etc., a trench 3 is formed on the silicon substrate 1, and an insulating film such as silicon dioxide film 4 is deposited thereof so as to fill the trench 3. Subsequently, the silicon dioxide film 4 on the silicon nitride film 2 as a convex part is polished and removed by CMP while leaving the silicon dioxide film 4 in the trench 3 as a concave part, whereby a device isolation structure in which, as shown in FIG. 1B, the silicon dioxide film 4 is embedded in the trench 3 is obtained.
In the CMP in such STI, when the silicon nitride film is exposed, polishing can be stopped from progressing by increasing the selection ratio of the silicon dioxide film to the silicon nitride film (i.e., the ratio of the polishing rate of silicon dioxide film to the polishing rate of silicon nitride film; hereinafter, sometimes simply referred to as “selection ratio”). In the polishing method using a silicon nitride film as a stopper film like this, a smoother surface can be obtained than the case of using the normal polishing method.
Thus, in the recent CMP technique, not only a high polishing rate for a silicon dioxide film is required in view of cost, but also a high selection ratio is important.
A method for improving polishing properties of a polishing agent has been proposed. Patent Document 1 discloses a polishing agent for a base material of a silicon-containing dielectric material, wherein the polishing agent contains, as an abrasive grain, a cerium oxide grain, etc. and contains at least one additive selected from an arylamine, a heterocyclic amine, an aminocarboxylic acid, a cyclic monocarboxylic acid and an unsaturated monocarboxylic acid.
With the polishing agent disclosed in Patent Document 1, the polishing rate of silicon dioxide film may be assured of a high value to a certain extent, but since the polishing rate of silicon nitride film is not sufficiently controlled, the selection ratio of silicon dioxide film to silicon nitride film is not high enough. In turn, the base material obtained has unsatisfactory planarity.
Patent Document 1: JP-T-2006-520530 (the term “JP-T” as used herein means a published Japanese translation of a PCT patent application) (WO2004/069947)